US 12,072,766 B2
Data protection and recovery
Marco Sforzin, Cernusco Sul Naviglio (IT); Paolo Amato, Treviglio (IT); and Joseph M. McCrate, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 4, 2022, as Appl. No. 17/959,412.
Prior Publication US 2024/0111629 A1, Apr. 4, 2024
Int. Cl. G06F 11/10 (2006.01)
CPC G06F 11/1096 (2013.01) 25 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a plurality of memory units; and
a controller communicatively coupled to the plurality of memory units respectively via a plurality of channels, the controller configured to:
read, from a first group of memory units of the plurality of memory units, a first user data block (UDB) as well as error correction information corresponding to the first UDB; and
perform, to perform an error correction operation on the first UDB using the error correction information and a parity check matrix including a plurality of bit patterns, one or more XOR operations between:
each bit of the first UDB and the error correction information having a particular bit value; and
a respective bit pattern of the plurality of bit patterns, wherein each bit pattern of the plurality of bit patterns includes one or more first bits to identify, among the first group of memory units, a memory unit corresponding to a bit position of the first UDB having an error.