| CPC G06F 11/108 (2013.01) [G06F 11/106 (2013.01)] | 25 Claims |
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1. An apparatus, comprising:
a memory array;
an interface controller configured to:
receive a plurality of data units comprising a first data unit comprising a first set of fields and a first set of parity bits associated with the first set of fields, and a second data unit comprising a second set of fields and a second set of parity bits associated with the second set of fields; and
generate, based at least in part on determining that the first data unit and the second data unit are associated with a common destination identifier, a protocol unit comprising first data from a subset of the first set of fields, a third set of parity bits generated using the first data, second data from a subset of the second set of fields, and a fourth set of parity bits generated using the second data, wherein generating the protocol unit is based at least in part on performing a first error checking process on the first data and the second data using the first set of parity bits and the second set of parity bits; and
a data storage controller coupled with the interface controller, wherein the data storage controller is configured to:
process the protocol unit to obtain a data storage unit based at least in part on performing a second error checking process on the first data and the second data using the third set of parity bits and the fourth set of parity bits, wherein the data storage unit comprises the first data, the second data, and a fifth set of parity bits generated using both the first data and the second data; and
transmit the data storage unit to the memory array.
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