US 12,072,762 B2
Error-handling management during copyback operations in memory devices
Patrick R. Khayat, San Diego, CA (US); and Vamsi Pavan Rayaprolu, Santa Clara, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 9, 2022, as Appl. No. 17/884,076.
Prior Publication US 2024/0054046 A1, Feb. 15, 2024
Int. Cl. G06F 11/10 (2006.01); G11C 29/08 (2006.01)
CPC G06F 11/1044 (2013.01) [G11C 29/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, to perform operations comprising:
selecting a source set of memory cells of the memory device, wherein the source set of memory cells are configured to store a first number of bits per memory cell;
performing a data integrity check on the source set of memory cells to obtain a data integrity metric value;
determining whether the data integrity metric value satisfies a threshold criterion;
responsive to determining that the data integrity metric value satisfies the threshold criterion, performing a first error-handling operation on the data stored on the source set of memory cells to generate corrected data;
responsive to determining that the first error-handling operation fails to correct the data, performing a second error-handling operation on the data; and
responsive to determining that the second error-handling operation corrects the data, causing the memory device to copy the corrected data to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell, wherein the second number of bits per memory cell is greater than the first number of bits per memory cell.