US 12,072,761 B2
Memory sub-system addressing for data and additional data portions
Daniele Balluchi, Cernusco sul Naviglio (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 2, 2022, as Appl. No. 17/831,436.
Prior Publication US 2023/0393930 A1, Dec. 7, 2023
Int. Cl. G06F 11/10 (2006.01); G06F 3/06 (2006.01)
CPC G06F 11/1004 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0688 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method, comprising:
accessing data written to a memory device in response to receipt of a first command configured according to a nondeterministic memory interface protocol,
wherein the first command is a compute express link (CXL) protocol compliant command;
converting an address associated with the first command to a second command configured according to a standardized deterministic memory interface protocol, wherein the second command is a DRAM accessible command and wherein converting the address associated with the first command comprises:
determining a sector in the memory device that includes a page of memory cells including the data;
assigning a sector value to identify the sector, wherein the sector comprises a number of most significant address bits, wherein the significance of the address bits is a physical capacity for which numbers and types of bits are to be used for which address correlation, and wherein the most significant address bits have the largest physical capacity; and
assigning remaining address bits of the number of address bits to different address bit modes, wherein the different address bit modes comprise less significant address bits than the sector;
accessing the page of memory cells of the memory device in which the data is written, and in which additional data portions associated with the data are written using the second command that comprises the converted address associated with the first command.