US 12,072,756 B2
Scalable machine check architecture
Vilas K. Sridharan, Boxborough, MA (US); Dean A. Liberty, Nashua, NH (US); Magiting Talisayon, Boxborough, MA (US); and Srikanth Masanam, Hyderabad (IN)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Jun. 30, 2022, as Appl. No. 17/854,710.
Prior Publication US 2024/0004744 A1, Jan. 4, 2024
Int. Cl. G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 11/14 (2006.01); G06F 12/02 (2006.01)
CPC G06F 11/0772 (2013.01) [G06F 11/0787 (2013.01); G06F 11/1405 (2013.01); G06F 12/0292 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a processing circuit; and
circuitry configured to perform, based on a first machine check architecture, error management together with the processing circuit; and
wherein, in response to processing an error, the processing circuit is configured to generate a target address of an access request, wherein the target address identifies a storage location in a memory of a remote partition configured to perform error management based on a second machine check architecture different from the first machine check architecture.