CPC G06F 11/0772 (2013.01) [G06F 11/0787 (2013.01); G06F 11/1405 (2013.01); G06F 12/0292 (2013.01)] | 20 Claims |
1. An apparatus comprising:
a processing circuit; and
circuitry configured to perform, based on a first machine check architecture, error management together with the processing circuit; and
wherein, in response to processing an error, the processing circuit is configured to generate a target address of an access request, wherein the target address identifies a storage location in a memory of a remote partition configured to perform error management based on a second machine check architecture different from the first machine check architecture.
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