CPC G06F 1/3206 (2013.01) [G06F 1/3275 (2013.01)] | 20 Claims |
8. A system-on-chip device, comprising:
a first power supply and a second power supply, at least one of the first power supply and the second power supply being disabled under a sleep mode in response to a status signal; and
a power management circuit configured to transmit a first power management signal to control an operation of the first power supply and the second power supply,
wherein the power management circuit comprises: a power detector configured to output the first power management signal according to the status signal and a first power supply signal associated with the first power supply, the power detector comprising a comparator circuit configured to detect the first power supply signal.
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