US 12,072,750 B2
Power management circuit, system-on-chip device, and method of power management
Chia-Chen Kuo, Hsinchu (TW); Yangsyu Lin, New Taipei (TW); Yu-Hao Hsu, Tainan (TW); Cheng Hung Lee, Hukou Township (TW); and Hung-Jen Liao, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 20, 2023, as Appl. No. 18/337,449.
Application 18/337,449 is a continuation of application No. 17/410,938, filed on Aug. 24, 2021, granted, now 11,726,539.
Claims priority of provisional application 63/154,524, filed on Feb. 26, 2021.
Prior Publication US 2023/0350477 A1, Nov. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/32 (2019.01); G06F 1/3206 (2019.01); G06F 1/3234 (2019.01)
CPC G06F 1/3206 (2013.01) [G06F 1/3275 (2013.01)] 20 Claims
OG exemplary drawing
 
8. A system-on-chip device, comprising:
a first power supply and a second power supply, at least one of the first power supply and the second power supply being disabled under a sleep mode in response to a status signal; and
a power management circuit configured to transmit a first power management signal to control an operation of the first power supply and the second power supply,
wherein the power management circuit comprises: a power detector configured to output the first power management signal according to the status signal and a first power supply signal associated with the first power supply, the power detector comprising a comparator circuit configured to detect the first power supply signal.