US 12,072,731 B2
Technique for clock alignment supporting reset isolation
Varun Singh, McKinney, TX (US); Rejitha Nair, Southlake, TX (US); John Chrysostom Apostol, Richardson, TX (US); Venkateswar Reddy Kowkutla, Allen, TX (US); and Santhanagopal Raghavendra, Dallas, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on May 15, 2023, as Appl. No. 18/317,190.
Application 18/317,190 is a continuation of application No. 17/537,150, filed on Nov. 29, 2021, granted, now 11,662,763.
Prior Publication US 2023/0280784 A1, Sep. 7, 2023
Int. Cl. G06F 1/12 (2006.01); G06F 1/08 (2006.01); G06F 1/10 (2006.01); H03K 21/08 (2006.01); H03K 19/20 (2006.01)
CPC G06F 1/12 (2013.01) [G06F 1/08 (2013.01); G06F 1/10 (2013.01); H03K 21/08 (2013.01); H03K 19/20 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit device comprising:
a clock selection circuit that includes:
a first input configured to receive a first clock signal;
a second input configured to receive a second clock signal;
a third input configured to receive a selection signal; and
an output, wherein the clock selection circuit is configured to provide an intermediate clock signal at the output based on either the first clock signal or the second clock signal based on the selection signal;
a gating circuit that includes:
a first input coupled to the output of the clock selection circuit;
a second input; and
an output configured to provide a third clock signal; and
an alignment circuit that includes an output coupled to the second input of the gating circuit, wherein the alignment circuit is configured to determine whether to provide an enable signal at the output of the alignment circuit such that the third clock signal is inhibited based on whether the intermediate clock signal transitions between being based on the second clock signal and being based on the first clock signal.