US 12,072,380 B2
JTAG registers with concurrent inputs
Antonino Mondello, Messina (IT); and Alberto Troia, Munich (DE)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Aug. 8, 2022, as Appl. No. 17/883,175.
Application 17/883,175 is a continuation of application No. 16/624,829, granted, now 11,408,935, previously published as PCT/IB2019/000434, filed on May 31, 2019.
Prior Publication US 2022/0382485 A1, Dec. 1, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G01R 31/3177 (2006.01); G06F 3/06 (2006.01); G06F 13/16 (2006.01); G11C 29/14 (2006.01); G11C 29/16 (2006.01); G11C 29/32 (2006.01)
CPC G01R 31/3177 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G06F 13/1668 (2013.01); G11C 29/14 (2013.01); G11C 29/16 (2013.01); G11C 29/32 (2013.01); G11C 2029/3202 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a host device;
a memory component coupled to the host device and comprising:
an array of memory cells; and
an interface comprising a boundary scan architecture, wherein the boundary scan architecture includes an instruction register configured to store data indicative of a presence of a test data input (TDI) signal; and
wherein the array of memory cells comprises a plurality of sub arrays each comprising:
a plurality of blocks of memory cells; and
a plurality of independently addressable extended pages in each block, each extended page including a group of data bits, address bits, and ECC bits.