CPC G01R 31/3177 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G06F 13/1668 (2013.01); G11C 29/14 (2013.01); G11C 29/16 (2013.01); G11C 29/32 (2013.01); G11C 2029/3202 (2013.01)] | 19 Claims |
1. An apparatus, comprising:
a host device;
a memory component coupled to the host device and comprising:
an array of memory cells; and
an interface comprising a boundary scan architecture, wherein the boundary scan architecture includes an instruction register configured to store data indicative of a presence of a test data input (TDI) signal; and
wherein the array of memory cells comprises a plurality of sub arrays each comprising:
a plurality of blocks of memory cells; and
a plurality of independently addressable extended pages in each block, each extended page including a group of data bits, address bits, and ECC bits.
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