US 12,072,374 B2
Detection pad structure for analysis in a semiconductor device
Jihoon Chang, Yongin-si (KR); Yeonjin Lee, Suwon-si (KR); Minjung Choi, Suwon-si (KR); and Jimin Choi, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 2, 2021, as Appl. No. 17/540,745.
Claims priority of application No. 10-2021-0046242 (KR), filed on Apr. 9, 2021.
Prior Publication US 2022/0326301 A1, Oct. 13, 2022
Int. Cl. G01R 31/28 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01)
CPC G01R 31/2884 (2013.01) [H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 2224/05097 (2013.01); H01L 2224/06515 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A detection pad structure in a semiconductor device, comprising:
a lower wiring on a substrate;
an upper wiring on the lower wiring, the upper wiring electrically connected to the lower wiring, the upper wiring including metal patterns and via contacts on the metal patterns, the metal patterns and via contacts stacked in a plurality of layers; and
a first pad pattern on the upper wiring, the first pad pattern electrically connected to the upper wiring,
wherein the semiconductor device includes an actual upper wiring including actual metal patterns and actual via contacts and a second pad pattern on the actual upper wiring, and the actual metal patterns and actual via contacts are stacked in a plurality of layers,
at least one of the metal patterns of each layer in the upper wiring has a minimum line width and a minimum space, the minimum line width and the minimum space of the at least one of the metal patterns in the upper wiring corresponding to a minimum line width and a minimum space of a corresponding actual metal pattern of the actual upper wiring, and
the metal patterns and via contacts of each layer in the upper wiring are regularly arranged and repeatedly arranged,
wherein upper surfaces of the first and second pad patterns have the same size, and
wherein the semiconductor device is a semiconductor chip or a semiconductor package including one or more detection pad structures arranged adjacent to an actual pad structure.