US 12,072,373 B2
Output terminal fault detection circuit
Kemal Safak Demirci, Dallas, TX (US); Shanmuganand Chellamuthu, Richardson, TX (US); and Qunying Li, Allen, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Mar. 6, 2023, as Appl. No. 18/117,516.
Application 18/117,516 is a continuation of application No. 17/168,528, filed on Feb. 5, 2021, granted, now 11,598,802.
Prior Publication US 2023/0204656 A1, Jun. 29, 2023
Int. Cl. G01R 31/28 (2006.01); H03F 3/45 (2006.01); H03K 5/24 (2006.01); H03K 19/20 (2006.01)
CPC G01R 31/2853 (2013.01) [H03F 3/45475 (2013.01); H03K 5/24 (2013.01); H03K 19/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a gain stage having an input and an output;
a first amplifier having an input and an output, the input of the first amplifier is coupled to the input of the gain stage;
a second amplifier having an input and an output, the input of the second amplifier is coupled to the output of the gain stage;
a comparison circuit having a first input, a second input, and a fault flag output, the first input coupled to the output of the first amplifier, the second input coupled to the output of the second amplifier.