US 12,071,701 B2
Plating system and method of plating wafer
Kuo-Lung Hou, Taichung (TW); and Ming-Hsien Lin, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu (TW)
Filed on Apr. 24, 2023, as Appl. No. 18/138,346.
Application 18/138,346 is a division of application No. 17/308,347, filed on May 5, 2021, granted, now 11,634,832.
Prior Publication US 2023/0257901 A1, Aug. 17, 2023
Int. Cl. C25D 21/12 (2006.01); C25D 5/54 (2006.01); C25D 7/12 (2006.01); C25D 17/00 (2006.01); C25D 17/02 (2006.01)
CPC C25D 21/12 (2013.01) [C25D 5/54 (2013.01); C25D 7/12 (2013.01); C25D 17/001 (2013.01); C25D 17/02 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of plating a wafer, comprising:
introducing, via an inlet of an electroplating chamber, a plating solution into a plating region within which the wafer is plated, wherein:
the plating region is defined by the electroplating chamber; and
the plating solution is used for plating the wafer;
inhibiting removal of the plating solution from the plating region by reflecting some of the plating solution using a barrier;
sensing a parameter of a plating process performed for plating the wafer with anode material of an anode within the electroplating chamber, wherein the parameter comprises at least one of a plating thickness, a pressure of the plating solution, or a direction of flow of the plating solution; and
adjusting a position of the barrier based upon the parameter, wherein the position of the barrier corresponds to at least one of a vertical position of the barrier or a horizontal position of the barrier.