| CPC H10B 43/50 (2023.02) [H01L 23/535 (2013.01); H01L 23/562 (2013.01); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 41/50 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02)] | 20 Claims |
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1. A semiconductor device comprising:
an upper-level layer on a substrate, the upper-level layer having a cell array region, a dummy region, and a cell contact region between the cell array region and the dummy region,
wherein the upper-level layer includes
a semiconductor layer;
a cell array structure on the semiconductor layer of the cell array region, the cell array structure including a first stack structure on the semiconductor layer and a second stack structure on the first stack structure, each of the first and second stack structures including a plurality of electrodes stacked and spaced apart from each other;
a first staircase structure on the semiconductor layer of the cell contact region, the plurality of electrodes extending from the cell array structure into the first staircase structure such that the cell array structure and the first staircase structure are connected to each other;
a vertical channel structure penetrating the cell array structure so as to be connected to the semiconductor layer;
a dummy structure in the dummy region, the dummy structure at the same level as the second stack structure, and the dummy structure including a plurality of first layers stacked and spaced apart from each other; and
cell contact plugs in the cell contact region and connected to the first staircase structure,
the cell contact region includes an overlapping region adjacent to the dummy region, and
the dummy structure vertically overlaps with at least a portion of the first staircase structure in the overlapping region.
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