US 11,744,070 B2
Semiconductor memory device
Toshiya Murakami, Meguro (JP); Kenji Tashiro, Kuwana (JP); Hidenori Miyagawa, Yokkaichi (JP); and Reiko Kitamura, Kuwana (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Mar. 12, 2021, as Appl. No. 17/199,660.
Claims priority of application No. 2020-157246 (JP), filed on Sep. 18, 2020.
Prior Publication US 2022/0093636 A1, Mar. 24, 2022
Int. Cl. H10B 43/27 (2023.01); H01L 23/522 (2006.01); H10B 41/27 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 23/5226 (2013.01); H10B 41/27 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a substrate;
a plurality of first conductive layers that are arranged in a first direction intersecting a surface of the substrate;
a first semiconductor layer that extends in the first direction and faces the plurality of first conductive layers;
a second semiconductor layer that extends in the first direction, faces the plurality of first conductive layers, and is spaced from the first semiconductor layer in a second direction intersecting the first direction;
a plurality of second conductive layers that are provided at a position overlapping the plurality of first conductive layers when viewed from the first direction, and are arranged in the first direction;
a plurality of third conductive layers that are provided at a position overlapping the plurality of first conductive layers when viewed from the first direction, are arranged in the first direction, and are arranged with the plurality of second conductive layers in the second direction;
a third semiconductor layer that extends in the first direction, faces the plurality of second conductive layers, and includes one end in the first direction connected to the first semiconductor layer;
a fourth semiconductor layer that extends in the first direction, faces the plurality of third conductive layers, and includes one end in the first direction connected to the second semiconductor layer;
a fourth conductive layer that is provided between the plurality of second conductive layers and the plurality of third conductive layers, and faces part of an outer peripheral surface of the third semiconductor layer; and
a fifth conductive layer that is provided between the plurality of second conductive layers and the plurality of third conductive layers, and is connected to the plurality of third conductive layers,
wherein, when a cross section that extends in the first direction and the second direction and includes part of the first semiconductor layer, part of the second semiconductor layer, part of the third semiconductor layer, and part of the fourth semiconductor layer is assumed to be a first cross section,
in the first cross section, a distance from a central axis of the third semiconductor layer to a central axis of the fourth semiconductor layer being larger than a distance from a central axis of the first semiconductor layer to a central axis of the second semiconductor layer.