CPC H10B 20/20 (2023.02) [G11C 17/16 (2013.01); G11C 17/18 (2013.01)] | 15 Claims |
1. A semiconductor circuit comprising:
a first memory element including a first terminal, a second terminal coupled to a first node, and a tunnel barrier film, and configured to store information by breaking the tunnel barrier film;
a first transistor including a drain coupled to the first node, a source, a gate, and a back gate coupled to a second node; and
a second transistor including a drain, a source coupled to the second node, and a gate coupled to the first node.
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