CPC H04W 28/0278 (2013.01) [H04L 1/1671 (2013.01); H04L 1/1835 (2013.01); H04W 8/22 (2013.01); H04W 28/04 (2013.01); H04W 28/22 (2013.01); H04W 28/065 (2013.01); H04W 84/12 (2013.01)] | 20 Claims |
1. An apparatus comprising:
memory circuitry; and
a processor comprising logic and circuitry configured to cause a first Enhanced Directional Multi-Gigabit (EDMG) wireless communication station (STA) to:
process a first field from a second EDMG STA, the first field comprising a first value to indicate a first length, the first length corresponding to a memory size at the second EDMG STA at a beginning of a Transmit Opportunity (TXOP);
process a second field from the second EDMG STA, the second field comprising a second value to indicate a second length, the second length comprising a maximal length of an Aggregate Medium Access Control (MAC) Protocol Data Unit (A-MPDU) transmission, the first value is less than or equal to the second value;
transmit a first A-MPDU to the second EDMG STA during the TXOP, a length of the first A-MPDU is not longer than the first length;
process a Block Acknowledgment (BlockAck) from the second EDMG STA to acknowledge the first A-MPDU, the BlockAck comprising a Receive Buffer Capacity (RBUFCAP) value based on an available memory size at the second EDMG STA; and
based on the RBUFCAP value, determine whether the first EDMG STA is to be allowed to transmit to the second STA a second A-MPDU having a length, which is not longer than the second length.
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