CPC H04L 41/0893 (2013.01) [G06F 15/17312 (2013.01); H04L 12/4633 (2013.01); H04L 41/0816 (2013.01); H04L 41/0853 (2013.01); H04L 41/0896 (2013.01); H04L 45/00 (2013.01); H04L 45/02 (2013.01); H04L 45/586 (2013.01); H04L 47/783 (2013.01); H04L 49/00 (2013.01); H04L 49/1546 (2013.01); H04L 49/3063 (2013.01); H04L 49/70 (2013.01); H04L 61/5007 (2022.05); G06F 11/07 (2013.01); H04L 2101/622 (2022.05)] | 20 Claims |
1. A method of processing packets associated with a logical switching element implemented by a plurality of physical switching elements executing on a plurality of host computers on which a plurality of machines executes, the method comprising:
at a first physical switching element that executes on a first host computer:
receiving a packet from a first machine that executes on the first host computer and that is associated with the logical switching element;
identifying, for the packet, a logical ingress port of the logical switching element that is associated with the packet;
using the logical ingress port to identify, for the packet, a logical egress port of the logical switching element that is associated with the packet;
using the logical egress port to identify, for the packet, a physical egress port of the first host computer to use to send the packet along to a second machine associated with the logical egress port; and
forwarding, from the identified physical egress port, the packet from the first host computer with an encapsulating header that stores the logical egress port.
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