US 11,743,123 B2
Managed switch architectures: software managed switches, hardware managed switches, and heterogeneous managed switches
Martin Casado, Portola Valley, CA (US); Teemu Koponen, San Francisco, CA (US); and Pankaj Thakkar, Cupertino, CA (US)
Assigned to NICIRA, INC., Palo Alto, CA (US)
Filed by Nicira, Inc., Palo Alto, CA (US)
Filed on Jun. 15, 2020, as Appl. No. 16/902,251.
Application 16/902,251 is a continuation of application No. 16/034,035, filed on Jul. 12, 2018, granted, now 10,686,663.
Application 16/034,035 is a continuation of application No. 15/076,634, filed on Mar. 21, 2016, granted, now 10,038,597, issued on Jul. 31, 2018.
Application 15/076,634 is a continuation of application No. 13/218,477, filed on Aug. 26, 2011, granted, now 9,306,875, issued on Apr. 5, 2016.
Application 13/218,477 is a continuation in part of application No. 13/177,536, filed on Jul. 6, 2011, granted, now 8,959,215, issued on Feb. 17, 2015.
Application 13/177,536 is a continuation of application No. 13/177,535, filed on Jul. 6, 2011, granted, now 8,750,164, issued on Jun. 10, 2014.
Application 13/177,535 is a continuation in part of application No. 13/177,538, filed on Jul. 6, 2011, granted, now 8,830,823, issued on Sep. 9, 2014.
Claims priority of provisional application 61/505,103, filed on Jul. 6, 2011.
Claims priority of provisional application 61/505,100, filed on Jul. 6, 2011.
Claims priority of provisional application 61/505,102, filed on Jul. 6, 2011.
Claims priority of provisional application 61/501,785, filed on Jun. 28, 2011.
Claims priority of provisional application 61/501,743, filed on Jun. 27, 2011.
Claims priority of provisional application 61/482,615, filed on May 4, 2011.
Claims priority of provisional application 61/482,616, filed on May 4, 2011.
Claims priority of provisional application 61/482,205, filed on May 3, 2011.
Claims priority of provisional application 61/466,453, filed on Mar. 22, 2011.
Claims priority of provisional application 61/429,753, filed on Jan. 4, 2011.
Claims priority of provisional application 61/429,754, filed on Jan. 4, 2011.
Claims priority of provisional application 61/361,913, filed on Jul. 6, 2010.
Claims priority of provisional application 61/361,912, filed on Jul. 6, 2010.
Prior Publication US 2020/0396130 A1, Dec. 17, 2020
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 12/24 (2006.01); H04L 12/26 (2006.01); H04L 12/46 (2006.01); H04L 12/54 (2022.01); H04L 12/713 (2013.01); H04L 12/911 (2013.01); H04L 12/931 (2013.01); H04L 12/933 (2013.01); H04L 12/935 (2013.01); G06F 9/38 (2018.01); G06F 11/07 (2006.01); G06F 15/16 (2006.01); G06F 15/173 (2006.01); H04L 41/0893 (2022.01); H04L 49/1546 (2022.01); H04L 45/586 (2022.01); H04L 49/00 (2022.01); H04L 47/783 (2022.01); H04L 45/00 (2022.01); H04L 41/0896 (2022.01); H04L 61/5007 (2022.01); H04L 45/02 (2022.01); H04L 41/0816 (2022.01); H04L 41/0853 (2022.01); H04L 101/622 (2022.01)
CPC H04L 41/0893 (2013.01) [G06F 15/17312 (2013.01); H04L 12/4633 (2013.01); H04L 41/0816 (2013.01); H04L 41/0853 (2013.01); H04L 41/0896 (2013.01); H04L 45/00 (2013.01); H04L 45/02 (2013.01); H04L 45/586 (2013.01); H04L 47/783 (2013.01); H04L 49/00 (2013.01); H04L 49/1546 (2013.01); H04L 49/3063 (2013.01); H04L 49/70 (2013.01); H04L 61/5007 (2022.05); G06F 11/07 (2013.01); H04L 2101/622 (2022.05)] 20 Claims
OG exemplary drawing
 
1. A method of processing packets associated with a logical switching element implemented by a plurality of physical switching elements executing on a plurality of host computers on which a plurality of machines executes, the method comprising:
at a first physical switching element that executes on a first host computer:
receiving a packet from a first machine that executes on the first host computer and that is associated with the logical switching element;
identifying, for the packet, a logical ingress port of the logical switching element that is associated with the packet;
using the logical ingress port to identify, for the packet, a logical egress port of the logical switching element that is associated with the packet;
using the logical egress port to identify, for the packet, a physical egress port of the first host computer to use to send the packet along to a second machine associated with the logical egress port; and
forwarding, from the identified physical egress port, the packet from the first host computer with an encapsulating header that stores the logical egress port.