US 11,743,072 B2
System and method of operating a system
Hans Jürgen Kollar, Bruchsal (DE)
Assigned to SEW-EURODRIVE GMBH & CO. KG, Bruchsal (DE)
Appl. No. 17/763,442
Filed by SEW-EURODRIVE GMBH & CO. KG, Bruchsal (DE)
PCT Filed Sep. 9, 2020, PCT No. PCT/EP2020/025402
§ 371(c)(1), (2) Date Mar. 24, 2022,
PCT Pub. No. WO2021/063537, PCT Pub. Date Apr. 8, 2021.
Claims priority of application No. 102019006875.0 (DE), filed on Oct. 2, 2019.
Prior Publication US 2022/0345329 A1, Oct. 27, 2022
Int. Cl. H04L 12/40 (2006.01); H03K 19/17784 (2020.01)
CPC H04L 12/40013 (2013.01) [H03K 19/17784 (2013.01); H04L 12/40039 (2013.01); H04L 2012/40215 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A system, comprising:
a first bus participant;
a successor; and
a controller connected to the first bus participant by a data bus;
wherein the first bus participant includes a first circuit arrangement between an output of the first bus participant and an input of the first bus participant;
wherein the successor includes a second circuit arrangement between an output of the successor and an input of the successor;
wherein the first and second circuit arrangements are of identical and/or similar configuration;
wherein the first and second circuit arrangements have a supply voltage terminal;
wherein the first circuit arrangement has a voltage sensing device adapted to sense a voltage applied to the output of the first circuit arrangement;
wherein a first resistor is arranged between the output of the first bus participant arrangement and the supply voltage terminal of the first bus participant;
wherein a second resistor is arranged between the input of the successor and a ground terminal;
wherein a first controllable semiconductor switch is adapted to selectively connect a third resistor between the input of the first bus participant and the supply voltage terminal of the successor, such that the third resistor is arranged in parallel with the first resistor, when connecting the successor to the first bus participant; and
wherein a second controllable semiconductor switch is adapted to selectively connect a fourth resistor between the output of the first bus subscriber and the supply voltage terminal of the successor, such that the fourth resistor is arranged in parallel with the third resistor, when connecting the successor to the first bus participant.