US 11,742,872 B2
Ad converter
Eizo Ichihara, Tokyo (JP); and Shintaro Kawazoe, Tokyo (JP)
Assigned to Asahi Kasei Microdevices Corporation, Tokyo (JP)
Filed by Asahi Kasei Microdevices Corporation, Tokyo (JP)
Filed on Apr. 26, 2022, as Appl. No. 17/728,985.
Claims priority of application No. 2021-078501 (JP), filed on May 6, 2021.
Prior Publication US 2022/0360274 A1, Nov. 10, 2022
Int. Cl. H03M 1/12 (2006.01); H03M 1/36 (2006.01); H03M 3/00 (2006.01); H03M 1/50 (2006.01); H03M 1/08 (2006.01)
CPC H03M 1/1245 (2013.01) [H03M 1/0854 (2013.01); H03M 1/361 (2013.01); H03M 1/50 (2013.01); H03M 3/39 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An AD converter, comprising:
an analog signal input circuit, configured to be input with an analog input signal, and output a first analog output signal based on the analog input signal and a second analog output signal based on the analog input signal at different timing;
an integral circuit, configured to integrate the first analog output signal and the second analog output signal to output the first integral signal and the second integral signal;
a predictive circuit, configured to predict an integral signal output after the output by the integral circuit based on the first integral signal and the second integral signal output by the integral circuit, and output a predictive integral signal; and
a quantization circuit, configured to generate a digital signal with the predictive integral signal quantized.