US 11,742,861 B2
Clock and data recovery lock detection circuit for verifying lock condition in presence of imbalanced early to late vote ratios
Kiarash Gharibdoust, Lonay (CH); and Ali Hormati, Ecublens Vaud (CH)
Assigned to KANDOU LABS SA, Lausanne (CH)
Filed by KANDOU LABS SA, Lausanne (CH)
Filed on Sep. 30, 2022, as Appl. No. 17/937,197.
Application 17/937,197 is a continuation of application No. 17/220,786, filed on Apr. 1, 2021, granted, now 11,463,092.
Prior Publication US 2023/0013802 A1, Jan. 19, 2023
Int. Cl. H03L 7/08 (2006.01); H03K 19/21 (2006.01); H03L 7/089 (2006.01); H03L 7/197 (2006.01)
CPC H03L 7/0807 (2013.01) [H03K 19/21 (2013.01); H03L 7/0891 (2013.01); H03L 7/197 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
sampling a data signal using a pair of samplers having decision thresholds corresponding to speculative decision feedback equalization (DFE) terms, responsively selecting an output of the pair of samplers as a data decision based on a prior data decision, and storing the data decision in a data history buffer;
detecting a transitional data pattern from data decision sequences in the data history buffer, and responsively selecting an output from another of the pair of samplers as an early-late vote in the data signal;
generating a first early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a first time interval;
generating a second early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a second time interval;
comparing the first and the second early-late vote measurements; and
outputting a clock and data recovery (CDR)-lock signal at least in part responsive to determining that the first and the second early-late vote measurements are within a predetermined threshold.