US 11,742,860 B2
Fabrication of a majority logic gate having non-linear input capacitors
Sasikanth Manipatruni, Portland, OR (US); Rafael Rios, Austin, TX (US); Neal Reynolds, Bremerton, WA (US); Ikenna Odinaka, Durham, NC (US); Robert Menezes, Portland, OR (US); Rajeev Kumar Dokania, Beaverton, OR (US); Ramamoorthy Ramesh, Moraga, CA (US); and Amrita Mathuriya, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Jun. 22, 2022, as Appl. No. 17/808,290.
Application 17/808,290 is a continuation of application No. 17/327,649, filed on May 21, 2021, granted, now 11,394,387.
Application 17/327,649 is a continuation of application No. 17/327,614, filed on May 21, 2021, granted, now 11,277,137, issued on Mar. 15, 2022.
Prior Publication US 2022/0393686 A1, Dec. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 19/00 (2006.01); H03K 19/23 (2006.01); H03K 19/21 (2006.01); H03K 19/185 (2006.01); H03K 19/0185 (2006.01); H03K 19/17784 (2020.01); H01L 49/02 (2006.01); H03K 19/003 (2006.01); H03K 19/164 (2006.01)
CPC H03K 19/23 (2013.01) [H01L 28/55 (2013.01); H03K 19/0013 (2013.01); H03K 19/00346 (2013.01); H03K 19/018521 (2013.01); H03K 19/164 (2013.01); H03K 19/17784 (2013.01); H03K 19/185 (2013.01); H03K 19/21 (2013.01); H03K 19/215 (2013.01); H01L 28/65 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first metal line of a first metal layer;
a second metal layer, wherein the second metal layer is higher than the first metal layer;
a first capacitor on the first metal line, wherein the first capacitor is further coupled to a first input line of the second metal layer;
a second capacitor on the first metal line, wherein the second capacitor is further coupled to a second input line of the second metal layer;
a third capacitor on the first metal line, wherein the third capacitor is further coupled to a third input line of the second metal layer, wherein the first capacitor, the second capacitor, and the third capacitor comprise non-linear polar material;
a via coupled to the first metal line, the via being under the first metal line; and
an active device having a gate electrode, wherein the gate electrode is coupled to the via.