US 11,742,835 B2
Semiconductor integrated circuit and semiconductor storage device
Masashi Nakata, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Mar. 14, 2022, as Appl. No. 17/693,864.
Claims priority of application No. 2021-147559 (JP), filed on Sep. 10, 2021.
Prior Publication US 2023/0079802 A1, Mar. 16, 2023
Int. Cl. H03K 3/017 (2006.01); H03K 3/86 (2006.01); G11C 8/18 (2006.01); G11C 7/22 (2006.01); H03K 3/0233 (2006.01)
CPC H03K 3/017 (2013.01) [G11C 7/222 (2013.01); G11C 8/18 (2013.01); H03K 3/0233 (2013.01); H03K 3/86 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor integrated circuit comprising:
a delay element group in which a plurality of first delay elements having a first delay amount are connected in series;
at least one flip-flop group including a plurality of flip-flops each of which an input is connected to an output of a corresponding first delay element among the plurality of first delay elements in the delay element group;
a second delay circuit configured to generate, from a first clock signal, a plurality of second clock signals each having a delay difference of a second delay amount smaller than the first delay amount; and
a variable delay circuit configured to set a third delay amount smaller than the second delay amount,
wherein the second delay circuit and the variable delay circuit are connected in series between a third clock output terminal and an input terminal of the flip-flop group.