US 11,742,673 B2
Power storage system and power storage device
Shunpei Yamazaki, Tokyo (JP); and Jun Koyama, Kanagawa (JP)
Assigned to SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Kanagawa-ken (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Mar. 17, 2020, as Appl. No. 16/821,011.
Application 16/821,011 is a continuation of application No. 15/434,832, filed on Feb. 16, 2017, granted, now 10,742,056.
Application 15/434,832 is a continuation of application No. 14/103,883, filed on Dec. 12, 2013, granted, now 9,577,446, issued on Feb. 21, 2017.
Claims priority of application No. 2012-272121 (JP), filed on Dec. 13, 2012.
Prior Publication US 2020/0220362 A1, Jul. 9, 2020
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/00 (2006.01); H02J 7/00 (2006.01); H01M 10/42 (2006.01)
CPC H02J 7/00047 (2020.01) [H02J 7/0031 (2013.01); H02J 7/00036 (2020.01); H01M 10/4257 (2013.01); H02J 7/00302 (2020.01)] 8 Claims
OG exemplary drawing
 
1. A power storage device comprising:
a power receiving circuit;
a power storage unit;
a first transistor between the power receiving circuit and the power storage unit;
a second transistor between the first transistor and the power storage unit;
a third transistor between the second transistor and the power storage unit; and
a control circuit electrically connected to a gate of the first transistor, a gate of the second transistor, a gate of the third transistor, and the power storage unit,
wherein the power receiving circuit is electrically connected to a one of a source and a drain of the first transistor,
wherein the other one of the source and the drain of the first transistor is electrically connected to a one of a source and a drain of the second transistor,
wherein the other one of the source and the drain of the second transistor is electrically connected to a one of a source and a drain of the third transistor,
wherein the other one of the source and the drain of the third transistor is electrically connected to the power storage unit,
wherein the second transistor is configured to serve as a protection switch for preventing overcharge of the power storage unit,
wherein the third transistor is configured to serve as a protection switch for preventing over-discharge of the power storage unit, and
wherein the control circuit includes:
a first memory circuit configured to hold data in a period during which power is supplied to the control circuit from the power storage unit; and
a second memory circuit configured to hold data in a period during which supply of the power to the control circuit from the power storage unit is stopped.