US 11,742,432 B2
Logic circuit and semiconductor device
Shunpei Yamazaki, Setagaya (JP); Jun Koyama, Sagamihara (JP); Masashi Tsubuku, Atsugi (JP); and Kosei Noda, Atsugi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Dec. 30, 2021, as Appl. No. 17/565,771.
Application 17/565,771 is a continuation of application No. 16/919,441, filed on Jul. 2, 2020, granted, now 11,302,824.
Application 16/919,441 is a continuation of application No. 16/787,562, filed on Feb. 11, 2020, granted, now 10,770,597, issued on Sep. 8, 2020.
Application 16/787,562 is a continuation of application No. 16/555,275, filed on Aug. 29, 2019, granted, now 10,593,810, issued on Mar. 17, 2020.
Application 16/555,275 is a continuation of application No. 14/936,305, filed on Nov. 9, 2015, granted, now 10,490,671, issued on Nov. 26, 2019.
Application 14/936,305 is a continuation of application No. 13/845,424, filed on Mar. 18, 2013, granted, now 10,211,344, issued on Feb. 19, 2019.
Application 13/845,424 is a continuation of application No. 12/901,057, filed on Oct. 8, 2010, granted, now 8,400,187, issued on Mar. 19, 2013.
Claims priority of application No. 2009-238914 (JP), filed on Oct. 16, 2009.
Prior Publication US 2022/0123149 A1, Apr. 21, 2022
Int. Cl. H01L 33/00 (2010.01); H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 27/02 (2006.01); H01L 21/66 (2006.01)
CPC H01L 29/7869 (2013.01) [H01L 27/0207 (2013.01); H01L 27/1225 (2013.01); H01L 29/78696 (2013.01); H01L 22/34 (2013.01); H01L 2924/0002 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A light-emitting device comprising:
a display portion, the display portion comprising:
a light-emitting element; and
a first transistor below and electrically connected to the light-emitting element, the first transistor comprising:
a first gate electrode layer over a substrate and a first insulating layer;
a second insulating layer over the first gate electrode layer;
an oxide semiconductor layer over the second insulating layer;
a first wiring layer electrically connected to the oxide semiconductor layer via a first opening provided in a third insulating layer which is provided over and in contact with the oxide semiconductor layer;
a second wiring layer electrically connected to the oxide semiconductor layer via a second opening provided in the third insulating layer; and
a second gate electrode layer over and overlapping with the oxide semiconductor layer and the first gate electrode layer,
wherein the oxide semiconductor layer comprises indium, gallium, and zinc,
wherein the first gate electrode layer and the second gate electrode layer are connected to each other, and
wherein, in a cross-sectional view, the first wiring layer and the second wiring layer do not overlap with the first gate electrode layer and the second gate electrode layer.