US 11,742,429 B2
Thin-film transistors with low contact resistance
Abhishek A. Sharma, Portland, OR (US); Van H. Le, Portland, OR (US); Li Huey Tan, Beaverton, OR (US); Tristan A. Tronic, Aloha, OR (US); Benjamin Chu-Kung, Boise, ID (US); Jack T. Kavalieros, Portland, OR (US); and Tahir Ghani, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 22, 2021, as Appl. No. 17/508,843.
Application 17/508,843 is a continuation of application No. 16/647,679, granted, now 11,189,733, previously published as PCT/US2018/013181, filed on Jan. 10, 2018.
Prior Publication US 2022/0045220 A1, Feb. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 29/20 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/78681 (2013.01) [H01L 29/0669 (2013.01); H01L 29/20 (2013.01); H01L 29/42384 (2013.01); H01L 29/66742 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A transistor comprising:
a gate electrode including one or more metals;
a gate dielectric on the gate electrode;
a layer on the gate dielectric, the layer including one or more metals, the layer also including oxygen;
a first contact structure on the layer, the first contact structure including one or more metals, a first portion of the layer between the first contact structure and the gate dielectric; and
a second contact structure on the layer, the second contact structure including one or more metals, a second portion of the layer between the second contact structure and the gate dielectric, wherein the first portion of the layer has a first thickness, the second portion of the layer has a second thickness, and a third portion of the layer between the first and second portions of the layer has a third thickness, the third thickness greater than the first thickness, and the third thickness the same as the second thickness.