US 11,742,380 B2
Select gate gate-induced-drain-leakage enhancement
Albert Fayrushin, Boise, ID (US); Haitao Liu, Boise, ID (US); and Matthew J. King, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 6, 2022, as Appl. No. 17/714,740.
Application 17/714,740 is a continuation of application No. 17/193,845, filed on Mar. 5, 2021, granted, now 11,362,175.
Prior Publication US 2022/0293726 A1, Sep. 15, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/16 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01); G11C 16/04 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H01L 29/0638 (2013.01) [G11C 16/0483 (2013.01); G11C 16/16 (2013.01); H01L 29/42328 (2013.01); H01L 29/42344 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/7889 (2013.01); H01L 29/7926 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a pillar disposed vertically as part of a memory array;
multiple transistors arranged along the pillar, with the pillar including a channel structure for each transistor of the multiple transistors;
a data line; and
a dissected contact between the data line and the channel structure, the dissected contact having one or more conductive regions contacting the channel structure and one or more non-conductive regions contacting the channel structure.