US 11,742,356 B2
Semiconductor device
Kazuya Uejima, Tokyo (JP); and Kazuhiro Koudate, Tokyo (JP)
Assigned to RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed by RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed on Mar. 4, 2022, as Appl. No. 17/687,141.
Application 17/687,141 is a continuation of application No. 17/131,455, filed on Dec. 22, 2020, granted, now 11,296,118.
Application 17/131,455 is a continuation of application No. 16/361,878, filed on Mar. 22, 2019, granted, now 10,879,271, issued on Dec. 29, 2020.
Claims priority of application No. 2018-077375 (JP), filed on Apr. 13, 2018.
Prior Publication US 2022/0189998 A1, Jun. 16, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/12 (2006.01); H03K 3/356 (2006.01); H03K 19/00 (2006.01); H03K 3/012 (2006.01); H03K 19/0185 (2006.01)
CPC H01L 27/1207 (2013.01) [H03K 3/012 (2013.01); H03K 3/35613 (2013.01); H03K 19/0013 (2013.01); H03K 19/018528 (2013.01)] 10 Claims
OG exemplary drawing
 
6. A semiconductor device comprising:
a first circuit connected between a first power supply line and a ground line;
a second circuit connected between a second power supply line and the ground line, wherein the second circuit receives a signal from the first circuit; and
a third circuit connected between a third power supply line and the ground line, wherein the third circuit receives a signal from the second circuit,
wherein the second circuit comprises a logic circuit and a switch element that are serially connected between the second power supply line and the ground line,
wherein the logic circuit comprises a first transistor of a first conductive type,
wherein the switch element comprises a second transistor of the first conductive type,
wherein the first transistor is formed in a semiconductor layer formed on a buried insulating layer, the buried insulating layer being formed on a support substrate,
wherein the second transistor includes a gate insulating film formed on a main surface of the support substrate, and
wherein the first transistor has a first channel formation region in the semiconductor layer, the second transistor has a second channel formation region in the support substrate, and an impurity concentration of the second channel formation region is higher than an impurity concentration of the first channel formation region.