US 11,742,329 B2
Semiconductor package
Jongho Park, Suwon-si (KR); Kyungsuk Oh, Suwon-si (KR); Hyunki Kim, Suwon-si (KR); Yongkwan Lee, Suwon-si (KR); Sangsoo Kim, Suwon-si (KR); Seungkon Mok, Suwon-si (KR); Junyoung Oh, Suwon-si (KR); and Changyoung Yoo, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Aug. 11, 2021, as Appl. No. 17/399,233.
Application 17/399,233 is a continuation of application No. 16/680,657, filed on Nov. 12, 2019, granted, now 11,101,243.
Claims priority of application No. 10-2019-0052206 (KR), filed on May 3, 2019.
Prior Publication US 2021/0375831 A1, Dec. 2, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/16 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 23/16 (2013.01); H01L 23/3185 (2013.01); H01L 23/49811 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/48227 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a substrate including a plurality of interconnections;
at least one chip on the substrate;
a plurality of first pads on the substrate, the plurality of first pads overlapping the at least one chip;
a plurality of bumps between the substrate and the at least one chip;
a plurality of second pads on an edge portion of a first side of the substrate, the plurality of second pads being electrically connected to the at least one chip through a plurality of first conductive wires;
an underfill that fills a space between the substrate and the at least one chip; and
a first dam on the substrate, the first dam overlapping the at least one chip.