US 11,742,317 B2
Process including a re-etching process for forming a semiconductor structure
Hui-Jung Tsai, Hsinchu (TW); Yun Chen Hsieh, Baoshan Township (TW); Jyun-Siang Peng, Hsinchu (TW); Tai-Min Chang, Taipei (TW); Yi-Yang Lei, Taichung (TW); Hung-Jui Kuo, Hsinchu (TW); and Chen-Hua Yu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Oct. 17, 2019, as Appl. No. 16/655,466.
Application 16/576,412 is a division of application No. 16/028,813, filed on Jul. 6, 2018, granted, now 10,522,501.
Application 16/655,466 is a continuation of application No. 16/576,412, filed on Sep. 19, 2019, granted, now 11,587,902.
Claims priority of provisional application 62/587,836, filed on Nov. 17, 2017.
Prior Publication US 2020/0051949 A1, Feb. 13, 2020
Int. Cl. H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2023.01); H01L 25/10 (2006.01); H01L 25/00 (2006.01)
CPC H01L 24/82 (2013.01) [H01L 23/5389 (2013.01); H01L 24/02 (2013.01); H01L 24/16 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/24 (2013.01); H01L 24/25 (2013.01); H01L 25/105 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/02313 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/18 (2013.01); H01L 2224/245 (2013.01); H01L 2224/24011 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/25171 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/82106 (2013.01); H01L 2224/92244 (2013.01); H01L 2224/97 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/15313 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
encapsulating a device die in an encapsulating material;
planarizing the encapsulating material and the device die;
forming a conductive feature over and electrically coupling to the device die, wherein the forming the conductive feature comprises:
forming an adhesion layer;
forming a metal region over the adhesion layer, wherein parts of the adhesion layer and the metal region form a metal line; and
after the metal region is formed, forming a via over the metal line; and
after the conductive feature is formed, performing a re-etching process, wherein in the re-etching process, the metal region is etched faster than the adhesion layer, wherein in the re-etching process, both of the metal line and the via are etched.