US 11,742,045 B2
Testing of comparators within a memory safety logic circuit using a fault enable generation circuit within the memory
Rohit Bhasin, New Delhi (IN); Shishir Kumar, Greater Noida (IN); Tanmoy Roy, Greater Noida (IN); and Deepak Kumar Bihani, Noida (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Apr. 5, 2021, as Appl. No. 17/222,119.
Application 17/222,119 is a continuation of application No. 16/702,744, filed on Dec. 4, 2019, granted, now 10,998,077.
Claims priority of provisional application 62/789,573, filed on Jan. 8, 2019.
Prior Publication US 2021/0225453 A1, Jul. 22, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/38 (2006.01); G11C 29/14 (2006.01)
CPC G11C 29/38 (2013.01) [G11C 29/14 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
comparison circuitry including a plurality of comparator circuits and a logic circuit for logically combining outputs of the comparator circuits to generate an output signal;
wherein each comparator circuit is configured to compare a bit of a first bus to a bit of a second bus; and
a testing circuit configured to test the comparator circuits of the comparison circuitry for a stuck-at-1 fault by:
applying a force signal to the first bus, wherein all bits of the force signal have a same logic state;
applying a testing signal to the second bus, wherein one bit of the testing signal has a first logic state and all other bits of the testing signal have a second logic state; and
monitoring for a logic state of the output signal indicative that the comparator circuit which received said one bit of the testing signal having the first logic state is in a stuck-at-1 fault condition.