CPC G11C 29/38 (2013.01) [G11C 29/14 (2013.01)] | 16 Claims |
1. An apparatus, comprising:
comparison circuitry including a plurality of comparator circuits and a logic circuit for logically combining outputs of the comparator circuits to generate an output signal;
wherein each comparator circuit is configured to compare a bit of a first bus to a bit of a second bus; and
a testing circuit configured to test the comparator circuits of the comparison circuitry for a stuck-at-1 fault by:
applying a force signal to the first bus, wherein all bits of the force signal have a same logic state;
applying a testing signal to the second bus, wherein one bit of the testing signal has a first logic state and all other bits of the testing signal have a second logic state; and
monitoring for a logic state of the output signal indicative that the comparator circuit which received said one bit of the testing signal having the first logic state is in a stuck-at-1 fault condition.
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