US 11,742,032 B2
Semiconductor memory device
Takeshi Hioka, Michida Tokyo (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Jan. 25, 2022, as Appl. No. 17/583,488.
Application 17/583,488 is a continuation of application No. 17/096,127, filed on Nov. 12, 2020, granted, now 11,270,775.
Application 17/096,127 is a continuation of application No. 16/535,327, filed on Aug. 8, 2019, granted, now 10,861,566, issued on Dec. 8, 2020.
Application 16/535,327 is a continuation of application No. 16/131,670, filed on Sep. 14, 2018, granted, now 10,418,114, issued on Sep. 17, 2019.
Application 16/131,670 is a continuation of application No. 15/693,407, filed on Aug. 31, 2017, granted, now 10,090,056, issued on Oct. 2, 2018.
Claims priority of application No. 2017-007572 (JP), filed on Jan. 19, 2017.
Prior Publication US 2022/0148660 A1, May 12, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/00 (2006.01); G11C 16/30 (2006.01); G11C 16/04 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/30 (2013.01) [G11C 16/0483 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a memory cell array including:
a first memory string including a first select transistor, a first memory cell transistor connected in series with the first select transistor, and a second memory cell transistor connected in series with the first memory cell transistor; and
a second memory string including a second select transistor, a third memory cell transistor connected in series with the second select transistor, and a fourth memory cell transistor connected in series with the third memory cell transistor;
a first word line connected to a gate of the first memory cell transistor and a gate of the third memory cell transistor;
a second word line connected to a gate of the second memory cell transistor and a gate of the fourth memory cell transistor;
a first selection gate line connected to a gate of the first select transistor;
a second selection gate line connected to a gate of the second select transistor;
a bit line connected to one end of the first memory string and one end of the second memory string; and
a source line connected to the other end of the first memory string and the other end of the second memory string,
wherein, during a read operation performed on the first memory cell transistor,
the second word line is boosted from a first voltage to a second voltage over a first time interval starting at a first time point and ending at a second time point, thereafter further boosted from the second voltage to a third voltage over a second time interval starting at the second time point and ending at a third time point, and thereafter maintained at the third voltage over a third time interval starting at the third time point and ending at a fourth time point,
the first selection gate line is boosted from the first voltage to the second voltage over the first time interval starting at the first time point,
the first word line is boosted from the first voltage to a fourth voltage, which is lower than the second voltage, over a fourth time interval, which is shorter than the first time interval, starting at the first time point and ending at a fifth time point, and thereafter set to a fifth voltage lower than the fourth voltage, and
the second selection gate line is boosted from the first voltage to a sixth voltage, which is lower than the second voltage, over the fourth time interval starting at the first time point, and thereafter decreased to a seventh voltage lower than the sixth voltage.