US 11,742,031 B2
Memory system including the semiconductor memory and a controller
Masanobu Shirakawa, Chigasaki (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Dec. 17, 2021, as Appl. No. 17/554,710.
Application 17/554,710 is a continuation of application No. 17/018,511, filed on Sep. 11, 2020, granted, now 11,244,730.
Application 17/018,511 is a continuation of application No. 16/563,045, filed on Sep. 6, 2019, granted, now 10,803,959, issued on Oct. 13, 2020.
Application 16/563,045 is a continuation of application No. 15/916,472, filed on Mar. 9, 2018, granted, now 10,453,536, issued on Oct. 22, 2019.
Claims priority of application No. 2017-181682 (JP), filed on Sep. 21, 2017.
Prior Publication US 2022/0108754 A1, Apr. 7, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 11/56 (2006.01); G11C 7/06 (2006.01); G11C 16/34 (2006.01); G11C 16/10 (2006.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); G11C 7/10 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 7/06 (2013.01); G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G11C 11/5671 (2013.01); G11C 16/10 (2013.01); G11C 16/3459 (2013.01); H10B 43/27 (2023.02); H10B 43/35 (2023.02); G11C 7/1039 (2013.01); G11C 16/0483 (2013.01); G11C 2211/562 (2013.01); G11C 2211/563 (2013.01); G11C 2211/5621 (2013.01); G11C 2211/5641 (2013.01); G11C 2211/5642 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A memory system comprising:
a semiconductor memory configured to store data; and
a controller configured to control the semiconductor memory,
wherein the semiconductor memory includes:
a plurality of first blocks each including a memory cell configured to store data of at least one bit,
a second block including a memory cell configured to store data of two or more bits, and
a sense amplifier including a first latch circuit and a second latch circuit,
wherein data is written into the semiconductor memory in units of a page by both a first write operation and a second write operation,
wherein in the first write operation,
the controller outputs a first write command specifying first data, a second write command specifying second data, and a third write command,
the semiconductor memory writes the first data into a first one of the first blocks, and the second data into a second one of the first blocks, and when receiving the third write command, the semiconductor memory writes data of at least two pages into the second block, using the first data and the second data,
wherein in the second write operation,
after issuing the third write command, the controller issues a first read command, a second read command, and a fourth write command, and
the semiconductor memory: reads the first data from the first one of the first blocks to the first latch circuit in response to the first read command; reads the second data from the second one of the first blocks to the second latch circuit in response to the second read command; and overwrites data of at least two pages in the second block written by the first write operation in response to the fourth write command, using the first data and the second data that are read to the first latch circuit and the second latch circuit, respectively,
wherein the fourth write command corresponds to a word line selected in response to the third write command,
a verify voltage that is used when the data of at least two pages is written in response to the fourth write command is higher than a verify voltage that is used when the data of at least two pages is written in response to the third write command, and
each of the first data and the second data includes each of a first bit and a second bit of the data of two or more bits to be written in the memory cell of the second block.