US 11,742,027 B2
Dynamic program erase targeting with bit error rate
Bruce A. Liikanen, Berthoud, CO (US); Michael Sheperek, Longmont, CO (US); and Larry J. Koudele, Erie, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 27, 2022, as Appl. No. 17/826,775.
Application 17/826,775 is a continuation of application No. 16/719,745, filed on Dec. 18, 2019, granted, now 11,361,825.
Prior Publication US 2022/0284967 A1, Sep. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/14 (2006.01); G11C 16/12 (2006.01); G11C 16/34 (2006.01); G06F 11/07 (2006.01); G11C 13/00 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01)
CPC G11C 16/14 (2013.01) [G06F 11/076 (2013.01); G06F 11/0727 (2013.01); G11C 13/00 (2013.01); G11C 16/12 (2013.01); G11C 16/3459 (2013.01); G11C 11/5635 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory array including memory cells; and
a processing device coupled to the memory array, the processing device to perform operations comprising:
selecting a program targeting rule based on values of a plurality of valley margins of programming distributions of the memory array;
performing, using the program targeting rule, a program erase targeting operation to adjust a voltage level associated with an erase distribution of the memory array;
determining a bit error rate (BER) of the memory array; and
in response to the BER not satisfying a BER control value, increasing the voltage level by a voltage step.