US 11,742,026 B2
Memory system including a memory controller and a memory chip that executes a two-stage program operation
Hideki Yamada, Yokohama Kanagawa (JP); Marie Takada, Yokohama Kanagawa (JP); and Masanobu Shirakawa, Chigasaki Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Jul. 20, 2022, as Appl. No. 17/869,081.
Application 17/869,081 is a continuation of application No. 16/802,428, filed on Feb. 26, 2020, granted, now 11,430,520.
Claims priority of application No. 2019-166886 (JP), filed on Sep. 13, 2019.
Prior Publication US 2022/0351780 A1, Nov. 3, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 11/56 (2006.01)
CPC G11C 16/10 (2013.01) [G06F 3/061 (2013.01); G06F 3/0658 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 16/0483 (2013.01); G11C 11/5628 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A memory system comprising:
a memory chip that includes:
a first word line,
a first plurality of memory cells connected to the first word line, each of the first plurality of memory cells being configured to store a plurality of bits of data corresponding to a plurality of threshold voltages,
a second word line, and
a second plurality of memory cells connected to the second word line, each of the second plurality of memory cells being configured to store a plurality of bits of data corresponding to the plurality of threshold voltages; and
a memory controller configured to perform a first write operation, a second write operation after the first write operation, a third write operation after the second write operation, and a fourth write operation after the third write operation, wherein
the first write operation includes transmitting a first command sequence to the memory chip to cause the memory chip to execute a first-stage program operation on the first plurality of memory cells,
the second write operation includes transmitting the first command sequence to the memory chip to cause the memory chip to execute the first-stage program operation on the second plurality of memory cells,
the third write operation includes transmitting a second command sequence to the memory chip to cause the memory chip to execute a second-stage program operation on the first plurality of memory cells,
the fourth write operation includes transmitting the second command sequence to the memory chip to cause the memory chip to execute a second-stage program operation on the second plurality of memory cells,
the first-stage program operation includes a first operation and a first part of a second operation after the first operation,
the second-stage program operation includes a second part of the second operation and no part of the first operation,
the first operation includes applying a program voltage a plurality of times while increasing the program voltage each of the times by a first step size, and
the first part of the second operation includes applying the program voltage a plurality of times while increasing the program voltage each of the times by a second step size smaller than the first step size.