	US 11,742,024 B2
	Memory device comprising source line coupled to multiple memory cells and method of operation
Yu-Der Chih, Hsin-Chu (TW); Cheng-Hsiung Kuo, Jhubei (TW); and Chung-Chieh Chen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsin-Chu (TW)
Filed on May 27, 2020, as Appl. No. 16/884,137.
Prior Publication US 2021/0375363 A1, Dec. 2, 2021
Int. Cl. G11C 16/10 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01); G11C 16/14 (2006.01)

CPC G11C 16/08 (2013.01) [G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 2216/04 (2013.01)]

20 Claims

1. A memory device, comprising:

a first memory cell comprising a first source/drain terminal, a first word line terminal, and a second source/drain terminal;

a second memory cell comprising a third source/drain terminal, a second word line terminal, and a fourth source/drain terminal;

a third memory cell comprising a fifth source/drain terminal, a third word line terminal, and a sixth source/drain terminal;

a fourth memory cell comprising a seventh source/drain terminal and a fourth word line terminal;

a first word line driver;

a first word line coupled to first word line driver, the first word line terminal, and the fourth word line terminal;

a second word line driver;

a second word line coupled to the second word line driver and the second word line terminal;

a third word line driver;

a third word line coupled to the third word line driver and the third word line terminal;

a first source line driver;

a first source line directly coupled to the first source/drain terminal, the third source/drain terminal, and the fifth source/drain terminal, wherein the first source line is also coupled to the first source line driver;

a second source line driver;

a second source line coupled to the seventh source/drain terminal and the second source line driver;

a first bit line coupled to the second source/drain terminal, the fourth source/drain terminal, and the sixth source/drain terminal; and

a memory device control circuit configured to:

in a program operation of the memory device, configure a first switch of the first source line driver to close to apply a first voltage to the first source line, resulting in the first voltage being applied to the first source/drain terminal, the third source/drain terminal, and the fifth source/drain terminal; and

in an erase operation of the memory device, configure a second switch of the first source line driver to close to apply a second voltage to the first source line, resulting in the second voltage being applied to the first source/drain terminal, the third source/drain terminal, and the fifth source/drain terminal.