US 11,742,020 B2
Storage device
Masahiko Nakayama, Kuwana Mie (JP); and Kazumasa Sunouchi, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Aug. 30, 2021, as Appl. No. 17/461,858.
Claims priority of application No. 2021-042453 (JP), filed on Mar. 16, 2021.
Prior Publication US 2022/0301621 A1, Sep. 22, 2022
Int. Cl. G11C 11/00 (2006.01); G11C 11/56 (2006.01); G11C 13/00 (2006.01)
CPC G11C 13/004 (2013.01) [G11C 13/003 (2013.01); G11C 13/0028 (2013.01); G11C 13/0069 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A storage device, comprising:
a memory cell array in which a plurality of memory cells respectively including a variable resistance memory element are divided into a plurality of memory blocks, the plurality of memory cells including a first memory cell and a second memory cell that are in the same memory block; and
a detection circuit, wherein
during a read operation in which the first memory cell is a read target, the detection circuit compares a first resistance value, which is a resistance value of the variable resistance memory element in the first memory cell, with a second resistance value, which is a resistance value of the variable resistance memory element in the second memory cell, and determines a value of data stored in the first memory cell based on whether or not the first resistance value is higher or lower than the second resistance value.