US 11,742,019 B2
Nonvolatile semiconductor memory device
Daisaburo Takashima, Yokohama (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 10, 2021, as Appl. No. 17/471,981.
Claims priority of application No. 2021-034802 (JP), filed on Mar. 4, 2021.
Prior Publication US 2022/0284953 A1, Sep. 8, 2022
Int. Cl. G11C 11/00 (2006.01); G11C 13/00 (2006.01)
CPC G11C 13/0009 (2013.01) [G11C 13/004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0069 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A nonvolatile semiconductor memory device comprising:
a bit line extending in a first direction;
a source line; and
a cell array including a plurality of string blocks, each of the string blocks being connected to the bit line at one end and connected to the source line at the other end, the string blocks being arranged with each other in the first direction, wherein
the string block has a plurality of local string blocks, the local string blocks being connected in series between the bit line and the source line by means of one or more local bit lines, one end of an upper most one of the local string blocks being connected to the bit line, the other one end of a lower most one of the local string blocks being connected to the source line,
the local string block has a plurality of local strings, the local strings being connected in parallel between the bit line and a uppermost one of the local bit lines, between two adjacent local bit lines, or between a lowermost one of the local bit lines and the source line,
the local string has a plurality of memory cells and a string selection transistor, the memory cells each including a cell transistor and a resistance change element, a gate terminal of the cell transistor being connected to a word line, the resistance change element being connected in parallel to both ends of the cell transistor, the memory cells being connected in series, a gate terminal of the string selection transistor being connected to a string selection line, the string selection transistors being further connected in series to the memory cells,
among the local string blocks, one local string block includes a block selection transistor and remaining local string blocks do not include a block selection transistor, a gate terminal of the block selection transistor of the one local string block being connected to a block selection line,
signals of two word lines connected to two adjacent string blocks in the first direction are common signals, and
signals of two block selection lines connected to the two adjacent string blocks are independent of each other.