US 11,742,018 B2
Signal generator for generating control signals for page buffer of memory device
Young Il Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Nov. 2, 2022, as Appl. No. 17/979,591.
Application 17/979,591 is a division of application No. 17/003,753, filed on Aug. 26, 2020, granted, now 11,521,671.
Claims priority of application No. 10-2020-0036672 (KR), filed on Mar. 26, 2020.
Prior Publication US 2023/0057251 A1, Feb. 23, 2023
Int. Cl. G11C 7/08 (2006.01); G11C 11/4091 (2006.01); G11C 16/26 (2006.01); G11C 16/24 (2006.01); G11C 16/06 (2006.01); G11C 16/04 (2006.01); G11C 7/10 (2006.01)
CPC G11C 11/4091 (2013.01) [G11C 7/08 (2013.01); G11C 16/06 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 7/1057 (2013.01); G11C 16/0483 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory block for storing data;
page buffers coupled to the memory block through bit lines; and
a signal generator configured to output a common sensing signal and a sensing signal included in page control signals for controlling the page buffers in response to an amplified voltage and a divided voltage generated through a single feedback loop,
wherein the page buffers are configured to precharge the bit lines, or sense a voltage or current in the bit lines in response to the page control signals including the common sensing signal and the sensing signal, and
wherein the signal generator comprises a divider circuit including at least one variable resistor and a voltage regulator, and configured to divide the amplified voltage to generate the divided voltage and a feedback voltage of the single feedback loop by the at least one variable resistor and the voltage regulator.