US 11,742,015 B2
Controller and memory system for refreshing memory based on fail bits and temperature
Hyun Ju Yoon, Icheon-si (KR); Min Kang, Icheon-si (KR); Dong Uc Ko, Icheon-si (KR); Dong Keun Kim, Icheon-si (KR); Young Su Oh, Icheon-si (KR); and Jun Hyun Chun, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jun. 7, 2021, as Appl. No. 17/340,922.
Claims priority of application No. 10-2020-0158149 (KR), filed on Nov. 23, 2020.
Prior Publication US 2022/0165329 A1, May 26, 2022
Int. Cl. G11C 11/406 (2006.01)
CPC G11C 11/40626 (2013.01) [G11C 11/40615 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a storage device including memory cells for storing data; and
a controller in communication with an external device and configured to control the storage device based on a request from the external device,
wherein the controller is configured to:
generate a read command in response to a self-refresh request received from the external device,
perform an error correction operation of read data read from the memory cells included in the storage device according to the read command,
detect fail bits included in the read data during the error correction operation,
count a number of fail bits detected during the error correction operation,
set a refresh period based on the number of fail bits and a temperature of the controller or the storage device, and perform a refresh operation of re-writing stored data in the memory cells based on the refresh period.