US 11,742,014 B2
Semiconductor device
Shunpei Yamazaki, Setagaya (JP); Kiyoshi Kato, Atsugi (JP); Hajime Kimura, Atsugi (JP); Atsushi Miyaguchi, Hadano (JP); and Tatsunori Inoue, Isehara (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Jun. 1, 2022, as Appl. No. 17/829,579.
Application 17/829,579 is a continuation of application No. 17/048,330, granted, now 11,355,176, previously published as PCT/IB2019/053299, filed on Apr. 22, 2019.
Claims priority of application No. 2018-088846 (JP), filed on May 2, 2018.
Prior Publication US 2022/0293159 A1, Sep. 15, 2022
Int. Cl. G11C 11/405 (2006.01); G06F 12/0893 (2016.01); H01L 27/12 (2006.01); H10B 12/00 (2023.01)
CPC G11C 11/405 (2013.01) [G06F 12/0893 (2013.01); H01L 27/1225 (2013.01); H10B 12/00 (2023.02)] 4 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a memory device and a control circuit,
wherein the memory device comprises a first memory circuit configured to be operated in a first memory level and a second memory circuit configured to be operated in a second memory level,
wherein the first memory level is a level with a higher access speed than the second memory level,
wherein the first memory circuit comprises a first transistor and the second memory circuit comprises a second transistor,
wherein each of the first transistor and the second transistor comprises an oxide semiconductor layer, a first gate and a second gate overlapped with the first gate, and
wherein the control circuit is configured to input a voltage to the second gate of the first transistor so that the first memory circuit is changed from the first memory level to the second memory level, and to input a voltage to the second gate of the second transistor so that the second memory circuit is changed from the second memory level to the first memory level.