CPC G11C 7/1063 (2013.01) [G11C 7/109 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01)] | 20 Claims |
1. A memory comprising:
a plurality of memory planes, each memory plane including (i) at least one corresponding memory array and (ii) one or more peripheral circuits dedicated to read and write operations associated with the at least one corresponding memory array and the corresponding memory plane;
an input/output (I/O) interface to receive memory commands and data from a host, and to output data to the host; and
one or more storage units configured to store, for each memory plane of the plurality of memory planes, (i) a corresponding plane ready (PRDY) signal indicating a busy or a ready state of the corresponding memory plane, and (ii) a corresponding plane array ready (PARDY) signal indicating a busy or a ready state of the corresponding memory array of the corresponding memory plane, such that a plurality of PRDY signals and a plurality of PARDY signals are stored corresponding to the plurality of memory planes,
wherein the memory is configured to execute (i) a first type of operation that engages multiple memory planes of the memory during at least a part of execution of the first type of operation, and (ii) a second type of operation that engages one memory plane, and not all of the plurality of memory planes, during at least a part of execution of the second type of operation, and
wherein
the first type of operation engages the memory arrays of the plurality of memory planes during at least the part of execution, such that the plurality of PARDY signals for the plurality of memory planes are simultaneously in the busy state, and
the second type of operation engages a memory array of one memory plane, and not all of the plurality of memory planes, during at least a part of execution, such that a PARDY signal of the one memory plane is in the busy state simultaneously with PARDY signals corresponding to memory planes without an ongoing operation in progress not being in the busy state.
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