US 11,741,352 B2
Area and power efficient implementation of resistive processing units using complementary metal oxide semiconductor technology
Tayfun Gokmen, Briarcliff Manor, NY (US); Seyoung Kim, White Plains, NY (US); Dennis M. Newns, Yorktown Heights, NY (US); and Yurii A. Vlasov, Champaign, IL (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Aug. 22, 2016, as Appl. No. 15/242,691.
Prior Publication US 2018/0053089 A1, Feb. 22, 2018
Int. Cl. G06N 3/06 (2006.01); G06N 3/065 (2023.01); G06N 3/084 (2023.01)
CPC G06N 3/065 (2023.01) [G06N 3/084 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A resistive processing unit (RPU) comprising:
a pair of transistors directly connected in series through a connecting pair of source/drain regions for pair of transistors providing an update function for a weight of a training methodology to the RPU, wherein the connecting pair of source/ drain regions are in direct contact with one another to provide a series connection without any further circuitry at the connecting pair of source/drain regions that provides the series connection between the pair of transistors;
a read transistor for reading said weight of the training methodology; and
a capacitor between and directly connecting a gate of the read transistor to the pair of transistors providing the update function for the RPU, the capacitor directly connected to one edge source/drain region of one transistor in the pair of transistors opposite connecting pair of source/drain regions, wherein only one node of the capacitor connects to a gate of the read transistor, and the capacitor connects to only one edge source/drain of one transistor in the pair of transistors opposite the connecting pair of source/drain regions, the capacitor stores said weight of training methodology for the RPU including greater than 1000 resistance states in increments assignable for machine learning using an artificial neural network.