US 11,741,347 B2
Non-volatile memory device including arithmetic circuitry for neural network processing and neural network system including the same
Joon-soo Kwon, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD.
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jul. 10, 2019, as Appl. No. 16/507,493.
Claims priority of application No. 10-2018-0164305 (KR), filed on Dec. 18, 2018.
Prior Publication US 2020/0193277 A1, Jun. 18, 2020
Int. Cl. G06N 3/063 (2023.01); G06F 7/544 (2006.01); G11C 16/26 (2006.01); G06F 7/57 (2006.01); G06N 3/045 (2023.01)
CPC G06N 3/063 (2013.01) [G06F 7/5443 (2013.01); G06F 7/57 (2013.01); G11C 16/26 (2013.01); G06N 3/045 (2023.01)] 17 Claims
OG exemplary drawing
 
1. A non-volatile memory device comprising:
a memory cell array to which an arithmetic internal data is written; and arithmetic circuitry configured to,
receive an arithmetic input data and the arithmetic internal data for an arithmetic operation of a neural network with the arithmetic internal data and the arithmetic input data in response to an arithmetic command, wherein the arithmetic internal data includes a first arithmetic internal data that is written to a first page of the memory cell array and is used as an operand of a first arithmetic operation of the neural network, and a second arithmetic internal data that is written to a second page of the memory cell array and is used as an operand of a second arithmetic operation of the neural network,
perform the arithmetic operation of the neural network using the arithmetic internal data and the arithmetic input data to generate an arithmetic result data, and
output the arithmetic result data of the arithmetic operation of the neural network, wherein the non-volatile memory device is configured to (i) receive an arithmetic information signal including a first address, and (ii) sequentially read the first arithmetic internal data and the second arithmetic internal data in response to the arithmetic command and the arithmetic information signal.