US 11,741,282 B2
Reinforcement learning-based adjustment of digital circuits
Siddhartha Nath, San Jose, CA (US); Vishal Khandelwal, Portland, OR (US); Yi-Chen Lu, Atlanta, GA (US); and Praveen Ghanta, Palo Alto, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Jan. 19, 2022, as Appl. No. 17/579,490.
Claims priority of provisional application 63/139,600, filed on Jan. 20, 2021.
Prior Publication US 2022/0229960 A1, Jul. 21, 2022
Int. Cl. G06F 30/3315 (2020.01); G06F 30/27 (2020.01)
CPC G06F 30/3315 (2020.01) [G06F 30/27 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method of adjusting a digital circuit design, the method comprising:
selecting a first path in the digital circuit design, the first path comprising a plurality of gates;
generating a k-hop neighborhood graph of the first path, where k is a positive integer;
encoding the k-hop neighborhood graph into a state vector;
applying a machine learning model to the state vector to determine an adjustment to be made on a first gate of the plurality of gates; and
changing the first gate based on the adjustment.