CPC G06F 13/26 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/0638 (2013.01); G06F 12/0866 (2013.01); G06F 13/14 (2013.01); G06F 13/1668 (2013.01); G06F 13/1684 (2013.01); G06F 13/28 (2013.01); G06F 13/364 (2013.01); G06F 13/4027 (2013.01); G06F 13/4068 (2013.01); G06F 13/4282 (2013.01); G06F 21/76 (2013.01); G06F 2213/0062 (2013.01); G06F 2213/40 (2013.01); G06F 2221/2103 (2013.01)] | 20 Claims |
1. A system, comprising:
a first die comprising:
a central processing unit (CPU); and
a first bridge; and
a second die electrically coupled to the first die by at least a subset of the die-to-die interconnects, wherein the second die comprises a second bridge,
wherein the second die is configured to provide a memory-mapped bus service to the CPU so that the memory-mapped bus service appears as though it is implemented on the first die to the CPU,
wherein a number of die-to-die interconnect signals selectively conveyed between the first bridge and the second bridge via the die-to-die interconnects is greater than a number of die-to-die interconnects,
wherein the first bridge, the second bridge and the die-to-die interconnects are configured to dynamic configure of a number of utilized die-to-die interconnects in the die-to-die interconnects, and
wherein the second die is configured to provide information specifying unused die-to-die interconnects and the first die is configured to set the number of utilized die-to-die interconnects based at least in part on the provided information.
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