US 11,741,032 B2
Directed interrupt for multilevel virtualization
Bernd Nerz, Boeblingen (DE); Marco Kraemer, Sindelfingen (DE); Christoph Raisch, Gerlingen (DE); Donald William Schmidt, Stone Ridge, NY (US); and Peter Dana Driever, Poughkeepsie, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Jun. 25, 2021, as Appl. No. 17/358,172.
Application 17/358,172 is a continuation of application No. 16/789,532, filed on Feb. 13, 2020, granted, now 11,138,139.
Claims priority of application No. 19157097 (EP), filed on Feb. 14, 2019.
Prior Publication US 2021/0318973 A1, Oct. 14, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/24 (2006.01); G06F 9/54 (2006.01)
CPC G06F 13/24 (2013.01) [G06F 9/542 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A computer program product for providing an interrupt signal, the computer program product comprising:
at least one computer readable storage medium readable by at least one processing circuit and storing instructions for performing a method comprising:
receiving, by a bus attachment device of a computer system from a first bus connected module of a plurality of bus connected modules operationally coupled to a plurality of processors via the bus attachment device, a first interrupt signal with an interrupt target ID, the interrupt target ID identifying one processor of the plurality of processors assigned for usage by a first guest operating system as a first target processor to handle the first interrupt signal, the first guest operating system being managed by a hypervisor, the hypervisor being independent of the bus attachment device;
checking, by the bus attachment device, that the first target processor is scheduled for usage by the first guest operating system; and
translating, by the bus attachment device based on the first target processor being scheduled for usage by the first guest operating system, the interrupt target ID to a logical processor ID and forwarding the first interrupt signal to the first target processor to handle, the forwarding using the logical processor ID resulting from the translating to address the first target processor directly.