US 11,740,993 B2
Debug trace of cache memory requests
Andrew J. Beaumont-Smith, Cambridge, MA (US); Sandeep Gupta, San Mateo, CA (US); Krishna C. Potnuru, San Jose, CA (US); and Matthias Knoth, Scotts Valley, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Nov. 30, 2021, as Appl. No. 17/538,939.
Claims priority of provisional application 63/239,349, filed on Aug. 31, 2021.
Prior Publication US 2023/0061419 A1, Mar. 2, 2023
Int. Cl. G06F 12/00 (2006.01); G06F 11/34 (2006.01); G06F 11/30 (2006.01); G06F 12/02 (2006.01)
CPC G06F 11/348 (2013.01) [G06F 11/3037 (2013.01); G06F 12/0223 (2013.01); G06F 2212/1008 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a plurality of processor circuits;
a cache memory circuit; and
a trace control circuit configured, in response to activation of a mode to record information indicative of program execution of at least one processor circuit of the plurality of processor circuits, to:
monitor memory requests transmitted between ones of the plurality of processor circuits and the cache memory circuit;
select a particular memory request of monitored memory requests using an arbitration algorithm;
allocate space in a trace buffer to the particular memory request; and
store, in the trace buffer, information associated with the particular memory request.