CPC G06F 11/348 (2013.01) [G06F 11/3037 (2013.01); G06F 12/0223 (2013.01); G06F 2212/1008 (2013.01)] | 20 Claims |
1. An apparatus, comprising:
a plurality of processor circuits;
a cache memory circuit; and
a trace control circuit configured, in response to activation of a mode to record information indicative of program execution of at least one processor circuit of the plurality of processor circuits, to:
monitor memory requests transmitted between ones of the plurality of processor circuits and the cache memory circuit;
select a particular memory request of monitored memory requests using an arbitration algorithm;
allocate space in a trace buffer to the particular memory request; and
store, in the trace buffer, information associated with the particular memory request.
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