US 11,740,970 B2
Dynamic adjustment of data integrity operations of a memory system based on error rate classification
Patrick Robert Khayat, San Diego, CA (US); James Fitzpatrick, Laguna Niguel, CA (US); AbdelHakim S. Alhussien, San Jose, CA (US); and Sivagnanam Parthasarathy, Carlsbad, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 2, 2020, as Appl. No. 16/807,056.
Prior Publication US 2021/0271549 A1, Sep. 2, 2021
Int. Cl. G06F 11/00 (2006.01); G06F 11/10 (2006.01); G06N 5/04 (2023.01); H03M 13/11 (2006.01); G11C 16/26 (2006.01); G06N 20/00 (2019.01); G11C 16/04 (2006.01)
CPC G06F 11/1076 (2013.01) [G06N 5/04 (2013.01); G06N 20/00 (2019.01); G11C 16/26 (2013.01); H03M 13/1102 (2013.01); G11C 16/0483 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A memory sub-system, comprising:
a processing device; and
at least one memory component, the memory component being enclosed in an integrated circuit package, the memory component having:
a group of memory cells formed on an integrated circuit die; and
a calibration circuit;
wherein the processing device is configured to transmit a command to the memory component to retrieve data from an address;
wherein in response to the command and during execution of the command, the calibration circuit is configured to measure signal and noise characteristics of the group of memory cells associated with encoded data retrieved from the group of memory cells;
wherein the memory sub-system has a data integrity classifier and a plurality of options available to process the encoded data;
wherein the data integrity classifier is configured to generate a prediction based on the signal and noise characteristics, wherein the prediction comprises a predicted error rate for decoding the encoded data retrieved during execution of the command; and
wherein the memory sub-system is configured to select an option from the plurality of options based on the prediction and decode the encoded data using the selected option.