US 11,740,965 B2
Memory system
Shunichi Igahara, Kamakura Kanagawa (JP); Yoshihisa Kojima, Kawasaki Kanagawa (JP); Takehiko Amaki, Yokohama Kanagawa (JP); and Suguru Nishikawa, Osaka Osaka (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Nov. 4, 2021, as Appl. No. 17/519,356.
Application 17/519,356 is a continuation of application No. 16/774,609, filed on Jan. 28, 2020, granted, now 11,194,656.
Claims priority of application No. 2019-104682 (JP), filed on Jun. 4, 2019.
Prior Publication US 2022/0058085 A1, Feb. 24, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 3/06 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 3/0679 (2013.01); G06F 11/1044 (2013.01); G06F 11/1056 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system comprising:
a memory;
a controller that includes a first encoder configured to encode first data having a first bit length and a first number of toggles, into second data having a second bit length longer than the first bit length and a second number of toggles smaller than the first number of toggles; and
a bus including a plurality of signal lines between the memory and the controller,
wherein the signal lines include a first signal line through which the controller transmits the second data to the memory and a second signal line through which the controller transmits a signal to notify the memory of a timing for receiving the second data.