US 11,740,802 B2
Error correction bypass for erased pages
John Martin Hayes, Mountain View, CA (US); Hari Kannan, Sunnyvale, CA (US); and Nenad Miladinovic, Campbell, CA (US)
Assigned to PURE STORAGE, INC., Santa Clara, CA (US)
Filed by PURE STORAGE, INC., Mountain View, CA (US)
Filed on Jul. 29, 2021, as Appl. No. 17/388,982.
Application 17/388,982 is a continuation of application No. 16/167,383, filed on Oct. 22, 2018, granted, now 11,099,749.
Application 16/167,383 is a continuation of application No. 14/842,687, filed on Sep. 1, 2015, granted, now 10,108,355, issued on Oct. 23, 2018.
Prior Publication US 2021/0357133 A1, Nov. 18, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); H04L 67/1097 (2022.01); G06F 11/10 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0652 (2013.01); G06F 3/0688 (2013.01); G06F 11/1068 (2013.01); H04L 67/1097 (2013.01); G06F 11/1076 (2013.01)] 20 Claims
OG exemplary drawing
 
8. A method, comprising:
establishing a connection between a storage device and one of a plurality of storage nodes of a storage cluster;
determining, for at least one page in memory of the storage device, that the at least one page is erased; and
bypassing error correction of the at least one page, responsive to determining that the at least one page is erased.