US 11,740,794 B2
Semiconductor memory device including a control circuit and at least two memory cell arrays
Masanobu Shirakawa, Chigasaki Kanagawa (JP); and Tokumasa Hara, Kawasaki Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Nov. 16, 2021, as Appl. No. 17/527,851.
Application 16/147,223 is a division of application No. 15/184,677, filed on Jun. 16, 2016, granted, now 10,120,584, issued on Nov. 6, 2018.
Application 17/527,851 is a continuation of application No. 16/883,560, filed on May 26, 2020, granted, now 11,226,742.
Application 16/883,560 is a continuation of application No. 16/147,223, filed on Sep. 28, 2018, granted, now 10,698,611, issued on Jun. 30, 2020.
Application 15/184,677 is a continuation of application No. 14/475,493, filed on Sep. 2, 2014, granted, now 9,396,775, issued on Jul. 19, 2016.
Claims priority of application No. 2014-051876 (JP), filed on Mar. 14, 2014.
Prior Publication US 2022/0075521 A1, Mar. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G11C 7/10 (2006.01); G06F 12/0875 (2016.01); G06F 13/16 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 7/24 (2006.01)
CPC G06F 3/061 (2013.01) [G06F 3/0634 (2013.01); G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/0875 (2013.01); G06F 13/16 (2013.01); G11C 7/1063 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/214 (2013.01); G06F 2212/452 (2013.01); G06F 2212/7203 (2013.01); G06F 2212/7207 (2013.01); G11C 7/24 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a semiconductor memory device including a first plane and a second plane, each of the first plane and the second plane including blocks; and
a memory controller configured to control the semiconductor memory device and to send a first command specifying an address in the first plane and a second command specifying an address in the second plane, wherein
the semiconductor memory device further includes:
a first cache configured to hold data transferred from the first plane;
a second cache configured to hold data transferred from the second plane; and
a controller configured to begin a first process on the first plane in response to the first command if the first and second caches are in the ready state when the first command is received and to begin a second process on the second plane according to the second command if at least the second cache is in the ready state,
the controller is further configured to determine whether a core operation associated with the second command can be performed simultaneously with a core operation associated with the first command if the second command is received while status information indicates the first cache is in the busy state and the second cache is in the ready state, the determination being made based on whether the core operation associated with the first command has started or not, and
the status information comprises a first status bit indicating whether the first plane is ready or busy and a second status bit indicating whether the second plane is ready or busy.